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Title: string Download
 Description: Serial Transceiver Design verilog language, a detailed Code
 Downloaders recently: [More information of uploader 迅雷]
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串口收发器\clock.v
..........\controller.v
..........\receiver.v
..........\sender.v
..........\test.bit
..........\test.v
..........\testbench.v
..........\top.ucf
    

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