- Category:
- VHDL-FPGA-Verilog
- Tags:
-
- File Size:
- 2kb
- Update:
- 2015-08-04
- Downloads:
- 0 Times
- Uploaded by:
- 王进才
Description: uwr write_trige
rxclk recv_finish
clk 50MHz
ref 25Mhz when bps=192
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uart19200.vhd