- Category:
- VHDL-FPGA-Verilog
- Tags:
-
- File Size:
- 4kb
- Update:
- 2015-08-10
- Downloads:
- 0 Times
- Uploaded by:
- 李娜
Description: A, B two serial data is converted to parallel data, and then enter the adder module, add the output.
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code\adder_16.vhd
....\M_4Bit28Bit.vhd
....\M_Ser2Par.vhd
code
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