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VHDL-FPGA-Verilog
Title:
key_detect
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Category:
VHDL-FPGA-Verilog
Tags:
[VHDL]
[源码]
File Size:
2kb
Update:
2015-09-08
Downloads:
0 Times
Uploaded by:
陈忠德
Description:
Verilog prepared by the simple key debounce module. Mainly synthesized by a combination of level examination module and module 10ms delay
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source\debounce_module.v ......\delay_module.v ......\detect_module.v source
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