Oscilloscope\readme.txt
............\Ready_for_download\B3_OSC_download.bit
............\Src\Constraint\oscilloscope.xdc
............\...\HDL_source\char_rom_mapping.v
............\...\..........\.lock\clock.xci
............\...\..........\clock_control.v
............\...\..........\debounce_0\debounce_0.dcp
............\...\..........\..........\debounce_0.veo
............\...\..........\..........\debounce_0.xci
............\...\..........\..........\debounce_0.xml
............\...\..........\..........\debounce_0_funcsim.v
............\...\..........\..........\debounce_0_funcsim.vhdl
............\...\..........\..........\debounce_0_stub.v
............\...\..........\..........\debounce_0_stub.vhdl
............\...\..........\..........\sim\debounce_0.v
............\...\..........\..........\..._1\new\debounce_tb.v
............\...\..........\..........\.ources_1\new\debounce.v
............\...\..........\..........\.ynth\debounce_0.v
............\...\..........\Fre_Calculate.v
............\...\..........\Fre_Vopp_mapping_rom.v
............\...\..........\IP_Catalog\XUP_debounce_1.0\component.xml
............\...\..........\..........\................\sim_1\new\debounce_tb.v
............\...\..........\..........\................\.ources_1\new\debounce.v
............\...\..........\..........\................\xgui\debounce_v1_0.tcl
............\...\..........\..........\XUP_debounce_1.0.zip
............\...\..........\..........\....vga_1.0\component.xml
............\...\..........\..........\...........\vga.v
............\...\..........\..........\...........\xgui\vga_v1_0.tcl
............\...\..........\..........\XUP_vga_1.0.zip
............\...\..........\..........\....xadc_1.0\component.xml
............\...\..........\..........\............\ip\xadc_wiz_0\xadc_wiz_0.xci
............\...\..........\..........\............\new\xadc.v
............\...\..........\..........\............\xgui\xadc_v1_0.tcl
............\...\..........\..........\XUP_xadc_1.0.zip
............\...\..........\OSC_top.v
............\...\..........\trigger.v
............\...\..........\vga_0\sim\vga_0.v
............\...\..........\.....\.ynth\vga_0.v
............\...\..........\.....\vga.v
............\...\..........\.....\vga_0.dcp
............\...\..........\.....\vga_0.veo
............\...\..........\.....\vga_0.xci
............\...\..........\.....\vga_0.xml
............\...\..........\.....\vga_0_funcsim.v
............\...\..........\.....\vga_0_funcsim.vhdl
............\...\..........\.....\vga_0_stub.v
............\...\..........\.....\vga_0_stub.vhdl
............\...\..........\vga_initials.v
............\...\..........\waveform_mapping_rom.v
............\...\..........\waveform_ram.v
............\...\..........\xadc_0\ip\xadc_wiz_0\xadc_wiz_0\simulation\functional\design.txt
............\...\..........\......\..\..........\..........\..........\timing\design.txt
............\...\..........\......\..\..........\xadc_wiz_0.v
............\...\..........\......\..\..........\xadc_wiz_0.xci
............\...\..........\......\..\..........\xadc_wiz_0.xdc
............\...\..........\......\..\..........\xadc_wiz_0.xml
............\...\..........\......\..\..........\xadc_wiz_0_ooc.xdc
............\...\..........\......\new\xadc.v
............\...\..........\......\sim\xadc_0.v
............\...\..........\......\.ynth\xadc_0.v
............\...\..........\......\xadc_0.dcp
............\...\..........\......\xadc_0.veo
............\...\..........\......\xadc_0.xci
............\...\..........\......\xadc_0.xml
............\...\..........\......\xadc_0_funcsim.v
............\...\..........\......\xadc_0_funcsim.vhdl
............\...\..........\......\xadc_0_stub.v
............\...\..........\......\xadc_0_stub.vhdl
............\...\prj\Oscilloscope.cache\wt\java_command_handlers.wdf
............\...\...\..................\..\synthesis.wdf
............\...\...\..................\..\synthesis_details.wdf
............\...\...\..................\..\webtalk_pa.xml
............\...\...\.............runs\.jobs\vrs_config_1.xml
............\...\