- Category:
- VHDL-FPGA-Verilog
- Tags:
-
- File Size:
- 1kb
- Update:
- 2015-09-25
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- 0 Times
- Uploaded by:
- 散散
Description: VHDL code for the FPGA DDS function, the output frequency is adjustable
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dds_clk.vhd