Description: Based on verilog 1588 v2 fpga implementation of the agreement, the project general code, for your reference
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pro_1588
........\ipcore
........\......\add_sub_48
........\......\..........\add_sub_48.v
........\......\..........\add_sub_48_ecp3.lpc
........\......\..........\add_sub_48_ecp3.v
........\......\cal_crc32
........\......\.........\cal_crc32.v
........\......\fifo_tran_64
........\......\............\fifo_tran_64.v
........\......\............\fifo_tran_64_ecp3.lpc
........\......\............\fifo_tran_64_ecp3.v
........\......\inf_dpram_512x16
........\......\................\inf_dpram_512x16.v
........\......\................\inf_dpram_512x16_ecp3.lpc
........\......\................\inf_dpram_512x16_ecp3.v
........\......\mac_crc32
........\......\.........\mac_crc32.v
........\......\pro_1588_dpram_256x8
........\......\....................\pro_1588_dpram_256x8.v
........\......\....................\pro_1588_dpram_256x8_ecp3.lpc
........\......\....................\pro_1588_dpram_256x8_ecp3.v
........\pro_1588_top.v
........\src
........\...\Abis_RX_1588.v
........\...\Abis_TX_1588.v
........\...\Debug_RX_1588.v
........\...\Debug_TX_1588.v
........\...\TX_1588_PRO.v
........\...\base_time.v
........\...\clk_2m5_gen.v
........\...\clk_2m5_trace.v
........\...\cpu_1588_inf.v
........\...\get_source_mac.v
........\...\mac_detect.v
........\...\pro_capture.v
........\...\rx_1588_pro.v
........\...\rx_lacp_1588_pro.v
........\...\rx_lacp_pro.v
........\...\speed_detect.v
........\...\test_2m5_clk_err.v
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