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Title: Lab2 Download
  • Category:
  • VHDL-FPGA-Verilog
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  • File Size:
  • 170kb
  • Update:
  • 2015-10-08
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  • Uploaded by:
  • tom
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Lab2\ARCH\REG_ARC-REG24B.vif
....\....\REG_ARC-REG8B.vif
....\....\SHIFTREG_ARC-SHIFTREG.vif
....\command.log
....\default.svf
....\ENTI\REG24B.vif
....\....\REG8B.vif
....\....\SHIFTREG.vif
....\filenames.log
....\REG24B-REG_ARC.syn
....\REG24B.mr
....\REG24B.syn
....\REG8B-REG_ARC.syn
....\reg8b.ddc
....\REG8B.mr
....\REG8B.syn
....\reg8b.vhd
....\reg8b.vhd.bak
....\SHIFTREG-SHIFTREG_ARC.syn
....\shiftreg.cr.mti
....\shiftreg.ddc
....\shiftreg.mpf
....\SHIFTREG.mr
....\SHIFTREG.syn
....\shiftreg.vhd
....\shiftreg_enable.vhd
....\shiftreg_gated.vhd
....\tb_shiftreg-enable.vhd
....\tb_shiftreg-gated2.vhd
....\tb_shiftreg.vhd
....\testvecs.in
....\transcript
....\vsim.wlf
....\work\@_opt\vopt1cimh0
....\....\.....\vopt2r4b31
....\....\.....\vopt34q0m1
....\....\.....\vopt67bfi2
....\....\.....\vopt7trs02
....\....\.....\vopt8d64f1
....\....\.....\vopt90kex0
....\....\.....\voptaj1sb0
....\....\.....\voptbsgw50
....\....\.....\voptc53iq0
....\....\.....\voptdhm791
....\....\.....\voptex7xt1
....\....\.....\vopthdtic2
....\....\.....\vopti08xt1
....\....\.....\voptjjm791
....\....\.....\voptk63iq0
....\....\.....\voptmsgw50
....\....\.....\voptni1sb0
....\....\.....\voptqyjex0
....\....\.....\voptra64f1
....\....\.....\voptsnrs02
....\....\.....\voptv0wbr2
....\....\.....\voptwj9n62
....\....\.....\voptx6q0m1
....\....\.....\voptys4b31
....\....\.....\voptzcimh0
....\....\.....\_deps
....\....\e\a.dat
....\....\.\a.dbs
....\....\.\a.prw
....\....\.\a.psm
....\....\.\_primary.dat
....\....\.\_primary.dbs
....\....\reg8b\reg_arc.dat
....\....\.....\reg_arc.dbs
....\....\.....\reg_arc.prw
....\....\.....\reg_arc.psm
....\....\.....\_primary.dat
....\....\.....\_primary.dbs
....\....\shiftreg\shiftreg_arc.dat
....\....\........\shiftreg_arc.dbs
....\....\........\shiftreg_arc.prw
....\....\........\shiftreg_arc.psm
....\....\........\_primary.dat
....\....\........\_primary.dbs
....\....\_info
....\....\_vmake
....\....\@_opt
....\....\e
....\....\reg8b
....\....\shiftreg
....\....\_temp
....\ARCH
....\ENTI
....\work
Lab2
    

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