Description: Verilig language I2C Mater described controller IP core, has been the practical application, suitable for FPGA I2C interface design applications. The IP core at Altera QII 15.1 integrated software environment and includes a processor based on the i2c NiosII Gen2 software driver code.
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i2c_master_controller\Docs\i2c_specs.pdf
.....................\....\I2C_tests.c
.....................\HAL\inc\i2c_opencores.h
.....................\...\src\component.mk
.....................\...\...\i2c_opencores.c
.....................\i2c_master_bit_ctrl.v
.....................\i2c_master_byte_ctrl.v
.....................\i2c_master_controller.v
.....................\i2c_master_controller_hw.tcl
.....................\i2c_master_controller_hw.tcl~
.....................\i2c_master_defines.v
.....................\i2c_master_top.v
.....................\i2c_opencores_sw.tcl
.....................\.nc\i2c_opencores_regs.h
.....................\timescale.v
.....................\HAL\inc
.....................\...\src
.....................\Docs
.....................\HAL
.....................\inc
i2c_master_controller
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