Title:
FPGA-digital-clock-and-stopwatch Download
- Category:
- MiddleWare
- Tags:
-
[VHDL]
[源码]
- File Size:
- 4.01mb
- Update:
- 2015-10-31
- Downloads:
- 0 Times
- Uploaded by:
- 刘东
Description: This is source code about FPGA,including digital clock and stopwatch,and you can use it according to your need.
To Search:
File list (Check if you may need any files):
数字时钟秒表\Shizhong
............\........\db
............\........\..\add_sub_lkc.tdf
............\........\..\add_sub_mkc.tdf
............\........\..\alt_u_div_kve.tdf
............\........\..\altsyncram_6s14.tdf
............\........\..\altsyncram_8s14.tdf
............\........\..\altsyncram_egq1.tdf
............\........\..\altsyncram_ggq1.tdf
............\........\..\altsyncram_gp14.tdf
............\........\..\cmpr_5cc.tdf
............\........\..\cmpr_8cc.tdf
............\........\..\cmpr_9cc.tdf
............\........\..\cntr_02j.tdf
............\........\..\cntr_gui.tdf
............\........\..\cntr_m4j.tdf
............\........\..\cntr_nbi.tdf
............\........\..\cntr_obi.tdf
............\........\..\cntr_pbi.tdf
............\........\..\cntr_qbi.tdf
............\........\..\cntr_sbi.tdf
............\........\..\decode_rqf.tdf
............\........\..\logic_util_heursitic.dat
............\........\..\lpm_divide_25m.tdf
............\........\..\lpm_divide_vcm.tdf
............\........\..\mux_7oc.tdf
............\........\..\mux_aoc.tdf
............\........\..\prev_cmp_Shizhong.qmsg
............\........\..\Shizhong.amm.cdb
............\........\..\Shizhong.asm.qmsg
............\........\..\Shizhong.asm.rdb
............\........\..\Shizhong.asm_labs.ddb
............\........\..\Shizhong.autoh_e4eb1.map.reg_db.cdb
............\........\..\Shizhong.autos_3e921.map.reg_db.cdb
............\........\..\Shizhong.cbx.xml
............\........\..\Shizhong.cmp.bpm
............\........\..\Shizhong.cmp.cdb
............\........\..\Shizhong.cmp.hdb
............\........\..\Shizhong.cmp.kpt
............\........\..\Shizhong.cmp.logdb
............\........\..\Shizhong.cmp.rdb
............\........\..\Shizhong.cmp_merge.kpt
............\........\..\Shizhong.cmp0.ddb
............\........\..\Shizhong.cmp1.ddb
............\........\..\Shizhong.cmp2.ddb
............\........\..\Shizhong.db_info
............\........\..\Shizhong.eda.qmsg
............\........\..\Shizhong.fit.qmsg
............\........\..\Shizhong.hier_info
............\........\..\Shizhong.hif
............\........\..\Shizhong.idb.cdb
............\........\..\Shizhong.lpc.html
............\........\..\Shizhong.lpc.rdb
............\........\..\Shizhong.lpc.txt
............\........\..\Shizhong.map.bpm
............\........\..\Shizhong.map.cdb
............\........\..\Shizhong.map.hdb
............\........\..\Shizhong.map.kpt
............\........\..\Shizhong.map.logdb
............\........\..\Shizhong.map.qmsg
............\........\..\Shizhong.map.rdb
............\........\..\Shizhong.map_bb.cdb
............\........\..\Shizhong.map_bb.hdb
............\........\..\Shizhong.map_bb.logdb
............\........\..\Shizhong.pre_map.cdb
............\........\..\Shizhong.pre_map.hdb
............\........\..\Shizhong.root_partition.map.reg_db.cdb
............\........\..\Shizhong.routing.rdb
............\........\..\Shizhong.rpp.qmsg
............\........\..\Shizhong.rtlv.hdb
............\........\..\Shizhong.rtlv_sg.cdb
............\........\..\Shizhong.rtlv_sg_swap.cdb
............\........\..\Shizhong.sgate.rvd
............\........\..\Shizhong.sgate_sm.rvd
............\........\..\Shizhong.sgdiff.cdb
............\........\..\Shizhong.sgdiff.hdb
............\........\..\Shizhong.sld_design_entry.sci
............\........\..\Shizhong.sld_design_entry_dsc.sci
............\........\..\Shizhong.smart_action.txt
............\........\..\Shizhong.sta.qmsg
............\........\..\Shizhong.sta.rdb
............\........\..\Shizhong.sta_cmp.8_slow.tdb
............\........\..\Shizhong.syn_hier_info
............\........\..\Shizhong.tis_db_list.ddb
............\........\..\sign_div_unsign_9kh.tdf
............\........\display.v
............\........\display.v.bak
............\........\fenpin.v
............\........\fenpin.v.bak
............\........\incremental_db
............\........\..............\compiled_partitions
............\........\..............\...................\Shizhong.autoh_e4eb1.map.cdb
............\........\..............\...................\Shizhong