- Category:
- VHDL-FPGA-Verilog
- Tags:
-
- File Size:
- 5kb
- Update:
- 2015-11-02
- Downloads:
- 0 Times
- Uploaded by:
- 刘东辉
Description: Digital lock specific requirements are as follows: 1. The system password is set using DIP switches sw [7: 0], is limited to four passwords sw [7: 6], sw [5: 4], sw [3: 2], sw [1: 0], respectively left to right 1,2,3,4 digit password every one of the range is limited to three numbers 0,1,2. 2. Use btn [2: 0] as input keys, btn [0], btn [1], btn [2] corresponding to each active input as a decimal number 0,1,2 (due to the limited number btn, the system does not support the unlock 3 containing numeric password). 3. Enter the password displayed on the 7-segment display tubes corresponding bit on, the order left to right, did not enter a password when no digital display numbers, enter the password only after the corresponding bit digital tube was lit. 4. Enter the same password stored password, unlock success, LED lights ld [7] is lit otherwise the lock fails, ld [0] is illuminated. 5. With a reset button btn [3]. After the keys back to the initial state.
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Digital Password Lock\bounce.vhd
.....................\clk_div.vhd
.....................\delaytime.vhd
.....................\display.vhd
.....................\main.vhd
.....................\state.vhd
.....................\test.ucf
Digital Password Lock
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