Title:
Four-bit-signed-number-division
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- Category:
- VHDL-FPGA-Verilog
- Tags:
-
- File Size:
- 4kb
- Update:
- 2015-11-02
- Downloads:
- 0 Times
- Uploaded by:
- 刘东辉
Description: Design of four sentinel signed integer divider (op = aibi), the software downloaded to the FPGA board through simulation to validate [the specific requirements] 1, using the clock as an input clock signal having a frequency of 50MHz 2, using a DIP switch sw7 ~ sw4 as dividend ai, which sw7 is MSB (high), sw4 for the LSB (low) 3, using DIP switches sw3 ~ sw0 divisor bi, where sw3 is MSB, sw0 for the LSB 4, using the buttons btn < 0> determining the signal as an input, press the Enter button at each change to get the output 5 to LED7 ~ 4 as the quotient op, LED3 is MSB, lights representing the bit is 1.6 to LED3 ~ 0 is the proceeds of the remainder, LED7 the MSB 7, if the divisor is zero, then led7 flashing (frequency custom, to the naked eye can distinguish prevail), led6 ~ 0 O
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File list (Check if you may need any files):
Four bit signed number division\bounce.vhd
...............................\clock_divider.vhd
...............................\division.vhd
...............................\lout.vhd
...............................\main.vhd
Four bit signed number division
