Description: Verilog an interesting state machine case, simple and easy to understand. Suitable for beginners. Is a small game, sparten board available.
Inclusion test.
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File list (Check if you may need any files):
One_step.pdf
one_step.v
One_step_ISE窗口.png
Three_step.pdf
three_step.v
Three_step_ISE窗口.png
Two_step.pdf
two_step.v
Two_step_ISE窗口.png
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