- Category:
- VHDL-FPGA-Verilog
- Tags:
-
- File Size:
- 1kb
- Update:
- 2014-11-23
- Downloads:
- 0 Times
- Uploaded by:
- 李仕意
Description: Using for E1 interface, support 2M frequency recovery and retime
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clock_retrive_lsy.vhd