Description: This procedure is a triangular wave generated procedures, it is practical, is one of the key software PWM to dial the software implementation
To Search:
File list (Check if you may need any files):
FPGA I_LOOP\cspwm.vhd
...........\ljys1.vhd
...........\triangle\triangle.asm.rpt
...........\........\triangle.done
...........\........\triangle.fit.eqn
...........\........\triangle.fit.rpt
...........\........\triangle.fit.summary
...........\........\triangle.flow.rpt
...........\........\triangle.map.eqn
...........\........\triangle.map.rpt
...........\........\triangle.map.summary
...........\........\triangle.pin
...........\........\triangle.pof
...........\........\triangle.qpf
...........\........\triangle.qsf
...........\........\triangle.qws
...........\........\triangle.sim.rpt
...........\........\triangle.sof
...........\........\triangle.tan.rpt
...........\........\triangle.tan.summary
...........\........\triangle.vhd
...........\........\triangle.vwf
...........\........\db\triangle.asm.qmsg
...........\........\..\triangle.asm_labs.ddb
...........\........\..\triangle.cbx.xml
...........\........\..\triangle.cmp.cdb
...........\........\..\triangle.cmp.hdb
...........\........\..\triangle.cmp.logdb
...........\........\..\triangle.cmp.qrpt
...........\........\..\triangle.cmp.rdb
...........\........\..\triangle.cmp.tdb
...........\........\..\triangle.cmp0.ddb
...........\........\..\triangle.dbp
...........\........\..\triangle.db_info
...........\........\..\triangle.eco.cdb
...........\........\..\triangle.eds_overflow
...........\........\..\triangle.fit.qmsg
...........\........\..\triangle.hier_info
...........\........\..\triangle.hif
...........\........\..\triangle.map.cdb
...........\........\..\triangle.map.hdb
...........\........\..\triangle.map.logdb
...........\........\..\triangle.map.qmsg
...........\........\..\triangle.pre_map.cdb
...........\........\..\triangle.pre_map.hdb
...........\........\..\triangle.psp
...........\........\..\triangle.rtlv.hdb
...........\........\..\triangle.rtlv_sg.cdb
...........\........\..\triangle.rtlv_sg_swap.cdb
...........\........\..\triangle.sgdiff.cdb
...........\........\..\triangle.sgdiff.hdb
...........\........\..\triangle.signalprobe.cdb
...........\........\..\triangle.sim.hdb
...........\........\..\triangle.sim.qmsg
...........\........\..\triangle.sim.qrpt
...........\........\..\triangle.sim.rdb
...........\........\..\triangle.sim.vwf
...........\........\..\triangle.sld_design_entry.sci
...........\........\..\triangle.sld_design_entry_dsc.sci
...........\........\..\triangle.syn_hier_info
...........\........\..\triangle.tan.qmsg
...........\sjxpwm\2014.7.16记录.txt
...........\......\ljys.vhd
...........\......\pwm.asm.rpt
...........\......\pwm.done
...........\......\pwm.fit.eqn
...........\......\pwm.fit.rpt
...........\......\pwm.fit.summary
...........\......\pwm.flow.rpt
...........\......\pwm.map.eqn
...........\......\pwm.map.rpt
...........\......\pwm.map.summary
...........\......\pwm.pin
...........\triangle\db
...........\triangle
...........\sjxpwm
FPGA I_LOOP
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