Description: VHDL for FPGA realization Communication Engineering 程汉明 based coding, and generate a graphical representation of the source
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haming\db\encode.db_info
......\..\encode.eco.cdb
......\..\encode.sld_design_entry.sci
......\..\logic_util_heursitic.dat
......\..\prev_cmp_encode.map.qmsg
......\..\prev_cmp_encode.qmsg
......\encode.asm.rpt
......\encode.bdf
......\encode.cdf
......\encode.done
......\encode.fit.rpt
......\encode.fit.smsg
......\encode.fit.summary
......\encode.flow.rpt
......\encode.map.rpt
......\encode.map.summary
......\encode.pin
......\encode.pof
......\encode.qpf
......\encode.qsf
......\encode.qws
......\encode.sof
......\encode.sta.rpt
......\encode.sta.summary
......\encode_assignment_defaults.qdf
......\incremental_db\compiled_partitions\encode.root_partition.cmp.dfp
......\..............\...................\encode.root_partition.cmp.kpt
......\..............\...................\encode.root_partition.cmp.logdb
......\..............\...................\encode.root_partition.map.dpi
......\..............\...................\encode.root_partition.map.kpt
......\..............\README
......\seg_look.bsf
......\seg_look.vhd
......\seg_look.vhd.bak
......\transcript
......\zy_encode.bsf
......\zy_encode.vhd
......\zy_encode.vhd.bak
......\incremental_db\compiled_partitions
......\db
......\incremental_db
haming
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