Title:
verilog-code-for-8bit-multiplier-using-vedic-algo
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- Category:
- Project Design
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- File Size:
- 11kb
- Update:
- 2014-12-17
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- Uploaded by:
- naz
Description: The vedic multiplier is used perform 16 bit multiplication using urdhva tiryakbhyam sutra. this produces the results with high speed and utilizes low power which is most efficient for the real time processors.
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verilog code for 8bit multiplier using vedic algoritham.docx
