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Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
Title: Adder Download
 Description: This code is used three methods to achieve adder verilog code, based on the success in the ISE Spartan6 simulation.
 Downloaders recently: [More information of uploader lihongye]
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File list (Check if you may need any files): 
 

adder1\adder1_test.v
......\adder1_ucf.ucf
......\adder_1.v
.....2\adder2.v
......\adder2_test.v
......\adder2_ucf.ucf
.....3\adder3.v
......\adder3_test.v
......\adder3_ucf.ucf
adder1
adder2
adder3

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