labmic_soc\firmware\lib\hal_io.c
..........\........\...\hal_uart.c
..........\........\...\stdint.h
..........\........\...\printf.c
..........\........\...\stdio.h
..........\........\...\hal_uart.h
..........\........\...\memory_map.h
..........\........\...\hal_io.h
..........\........\...\.deps\pic.Po
..........\........\...\.....\hal_io.Po
..........\........\...\.....\printf.Po
..........\........\...\.....\hal_uart.Po
..........\........\led_keyboard.c
..........\........\Makefile
..........\.pga\cores\memory\dpram32_coregen.v
..........\....\.....\......\mem_delay_gen.v
..........\....\.....\......\medfifo.v
..........\....\.....\......\ram_harvard_coregen.v
..........\....\.....\......\longfifo.v
..........\....\.....\......\shortfifo.v
..........\....\.....\......\srl.v
..........\....\.....\aemb\rtl\verilog\aeMB_sim.v
..........\....\.....\....\...\.......\aeMB_edk32_virtex6.v
..........\....\.....\....\...\.......\aeMB_ibuf_virtex6.v
..........\....\.....\....\...\.......\aeMB_regf.v
..........\....\.....\....\...\.......\aeMB_core_virtex6.v
..........\....\.....\....\...\.......\aeMB_ctrl.v
..........\....\.....\....\...\.......\aeMB_core.v
..........\....\.....\....\...\.......\aeMB_bpcu.v
..........\....\.....\....\...\.......\aeMB_xecu.v
..........\....\.....\....\...\.......\aeMB_core_BE.v
..........\....\.....\....\...\.......\aeMB_edk32.v
..........\....\.....\....\...\.......\aeMB_ibuf.v
..........\....\.....\....\...\.......\aeMB_core_BE_virtex6.v
..........\....\.....\....\sw\c\endian-test.c
..........\....\.....\....\..\.\aeMB_testbench.c
..........\....\.....\....\..\.\libaemb.h
..........\....\.....\....\..\gccrom
..........\....\.....\....\.im\verilog\aemb2.v
..........\....\.....\....\...\.......\edk32.v
..........\....\.....\....\...\iversim
..........\....\.....\....\...\CODE_DEBUG.sav
..........\....\.....\....\...\cversim
..........\....\.....\....\doc\aeMB_datasheet.pdf
..........\....\.....\Makefile.srcs
..........\....\.....\bus\wb_1master.v
..........\....\.....\example\wishbone_example.v
..........\....\.....\control\system_control.v
..........\....\.....\.......\ram_loader_uart.v
..........\....\.....\uart\simple_uart_rx.v
..........\....\.....\....\simple_uart.v
..........\....\.....\....\simple_uart_tx.v
..........\....\models\xlnx_glbl.v
..........\....\......\uart_rx.v
..........\....\......\RAMB16_S36_S36.v
..........\....\......\FIFO_GENERATOR_V4_3.v
..........\....\......\M24LC024B.v
..........\....\......\Makefile.srcs
..........\....\......\math_real.v
..........\....\......\SRL16E.v
..........\....\......\SRLC16E.v
..........\....\......\uart_host.v
..........\....\......\M24LC02B.v
..........\....\......\BUFG.v
..........\....\......\host_bootloader_model.v
..........\....\......\BLK_MEM_GEN_V4_1.v
..........\....\......\BLK_MEM_GEN_V6_1.v
..........\....\......\MULT18X18S.v
..........\....\......\FIFO_GENERATOR_V6_1.v
..........\....\coregen\ram_xlnx_4k_dp.gise
..........\....\.......\coregen.cgc
..........\....\.......\ram_xlnx_4k_dp_flist.txt
..........\....\.......\clk_xlnx_100M.v
..........\....\.......\clk_xlnx_100M_flist.txt
..........\....\.......\ram_xlnx_4k_dp.v
..........\....\.......\clk_xlnx_100M.xaw
..........\....\.......\ram_xlnx_4k_dp.ncf
..........\....\.......\ram_xlnx_4k_dp.ngc
..........\....\.......\ram_xlnx_4k_dp.veo
..........\....\.......\Makefile.srcs
..........\....\.......\coregen.log
..........\....\.......\blk_mem_gen_ds512.pdf
..........\....\.......\xaw2verilog.log
..........\....\.......\clk_xlnx_100M_arwz.ucf
..........\....\.......\_xmsgs\pn_parser.xmsgs
..........\....\.......\ram_xlnx_4k_dp.xise
..........\....\.......\ram_xlnx_4k_dp.xco
..........\....\.......\ram_xlnx_4k_dp_xmdf.tcl
..........\....\.......\coregen.cgp
..........\....\.......\blk_mem_gen_readme.txt
..........\....\testbench\wb_soc.do
..........\....\.........\Makefile
..........\....\.oplevel\wb_soc\wb_soc_spartan3.impact
..........\....\........\......\wb_soc_spartan3.cdf
..........\....\........\......\wb_soc_spartan3.ucf
..........\....\........\......\wb_soc_si