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Title: CPU Download
 Description: Using Verilog HDL language to complete a simple multi-cycle MIPS microprocessor design
 Downloaders recently: [More information of uploader 胡森]
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File list (Check if you may need any files):
 

demo.coe
eunit.v
iunit.v
mips_cpu.v
munit.v
mux_2to1.v
Registers.v
ROM_array.v
top_tb.v
transcript
adder_4bits.v
adder_4bits_0.v
adder_32bits.v
ALU.v
ALU_tb.v
ALUControl.v
cunit.v
cunit_tb.v
D_32bits.v
    

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