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VHDL-FPGA-Verilog
Title:
clk_div_N
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Category:
VHDL-FPGA-Verilog
Tags:
[VHDL]
[源码]
File Size:
1kb
Update:
2015-01-03
Downloads:
0 Times
Uploaded by:
李亮
Description:
Program can be any even divided clock using Verilog language. Been verified in quartus ii and simulation
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clk_div_N.v
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