greybox_tmp
...........\cbx_args.txt
Sdram_WR_FIFO.qip
sdram_pll.qip
c5_pin_model_dump.txt
DE1_SoC_CAMERA.v
Sdram_RD_FIFO.qip
DE1_SoC_CAMERA.qws
DE1_SoC_CAMERA.pin
DE1_SoC_CAMERA.fit.summary
DE1_SoC_CAMERA.map.summary
PLLJ_PLLSPE_INFO.txt
DE1_SoC_CAMERA.sdc
DE1_SoC_CAMERA.jdi
DE1_SoC_CAMERA.done
qmegawiz_errors_log.txt
DE1_SoC_CAMERA.qsf
DE1_SoC_CAMERA.fit.smsg
DE1_SoC_CAMERA.sta.summary
DE1_SoC_CAMERA_assignment_defaults.qdf
Sdram_Control
.............\Sdram_Params.h
.............\Sdram_WR_FIFO.v
.............\Sdram_WR_FIFO.qip
.............\Sdram_Control.v
.............\Sdram_RD_FIFO.qip
.............\control_interface.v
.............\command.v
.............\sdr_data_path.v
.............\Sdram_RD_FIFO.v
sdram_pll.xml
DE1_SoC_CAMERA.sof
demo_batch
..........\DE1_SoC_CAMERA.bat
..........\DE1_SoC_CAMERA.sof
DE1_SoC_CAMERA.qpf
v
.\sdram_pll.bsf
.\vga_pll_wave0.jpg
.\sdram_pll.qip
.\vga_pll.ppf
.\sdram_pll.v
.\sdram_pll.cmp
.\Line_Buffer1.bsf
.\sdram_pll_sim.f
.\VGA_Controller.v
.\sdram_pll.sip
.\Reset_Delay.v
.\I2C_CCD_Config.v
.\Line_Buffer1.v
.\sdram_pll
.\.........\sdram_pll_0002.qip
.\.........\sdram_pll_0002.v
.\sdram_pll.spd
.\RAW2RGB.v
.\sdram_pll_sim
.\.............\sdram_pll.vo
.\.............\mentor
.\.............\......\msim_setup.tcl
.\.............\synopsys
.\.............\........\vcs
.\.............\........\...\vcs_setup.sh
.\.............\........\vcsmx
.\.............\........\.....\vcsmx_setup.sh
.\.............\........\.....\synopsys_sim.setup
.\.............\cadence
.\.............\.......\hdl.var
.\.............\.......\ncsim_setup.sh
.\.............\.......\cds.lib
.\.............\aldec
.\.............\.....\rivierapro_setup.tcl
.\sdram_pll.ppf
.\SEG7_LUT.v
.\CCD_Capture.v
.\vga_pll_waveforms.html
.\SEG7_LUT_6.v
.\Line_Buffer1.qip
.\I2C_Controller.v
.\vga_pll.bsf
Line_Buffer1.qip
hc_output
.........\DE1_SoC_CAMERA.names_drv_tbl