CD1_EDGE_DECT\FPGA_CODE\CD1_EDGE_DECT.asm.rpt
.............\.........\CD1_EDGE_DECT.cdf
.............\.........\CD1_EDGE_DECT.done
.............\.........\CD1_EDGE_DECT.fit.rpt
.............\.........\CD1_EDGE_DECT.fit.smsg
.............\.........\CD1_EDGE_DECT.fit.summary
.............\.........\CD1_EDGE_DECT.flow.rpt
.............\.........\CD1_EDGE_DECT.map.rpt
.............\.........\CD1_EDGE_DECT.map.smsg
.............\.........\CD1_EDGE_DECT.map.summary
.............\.........\CD1_EDGE_DECT.pin
.............\.........\CD1_EDGE_DECT.pof
.............\.........\CD1_EDGE_DECT.qpf
.............\.........\CD1_EDGE_DECT.qsf
.............\.........\CD1_EDGE_DECT.sof
.............\.........\CD1_EDGE_DECT.sta.rpt
.............\.........\CD1_EDGE_DECT.sta.summary
.............\.........\greybox_tmp\cbx_args.txt
.............\.........\MY_CODE\AUDIO_DAC.v
.............\.........\.......\CD1_EDGE_DECT.v
.............\.........\.......\CMOS_Capture.v
.............\.........\.......\Curve_Averaging.v
.............\.........\.......\I2C_Controller.v
.............\.........\.......\I2C_OV5620_Config.v
.............\.........\.......\lcd_display.v
.............\.........\.......\Line_Buffer.v
.............\.........\.......\MAC_3.v
.............\.........\.......\mif\osd.mif
.............\.........\.......\...\OV_DISP.mif
.............\.........\.......\...\vip.mif
.............\.........\.......\osd_rom.qip
.............\.........\.......\osd_rom.v
.............\.........\.......\PLL.v
.............\.........\.......\RAW2RGB.v
.............\.........\.......\Reset_Delay.v
.............\.........\.......\RGB2Mono.v
.............\.........\.......\Sdram_Control_4Port\command.v
.............\.........\.......\...................\control_interface.v
.............\.........\.......\...................\Sdram_Control_4Port.v
.............\.........\.......\...................\Sdram_Params.h
.............\.........\.......\...................\Sdram_PLL.bsf
.............\.........\.......\...................\Sdram_PLL.ppf
.............\.........\.......\...................\Sdram_PLL.qip
.............\.........\.......\...................\Sdram_PLL.v
.............\.........\.......\...................\Sdram_RD_FIFO.qip
.............\.........\.......\...................\Sdram_RD_FIFO.v
.............\.........\.......\...................\Sdram_WR_FIFO.qip
.............\.........\.......\...................\Sdram_WR_FIFO.v
.............\.........\.......\...................\sdr_data_path.v
.............\.........\.......\.obel\center.v
.............\.........\.......\.....\LineBuffer_3.v
.............\.........\.......\.....\MAC_sobel.v
.............\.........\.......\.....\PA_3.v
.............\.........\.......\.....\Sobel.v
.............\.........\.......\.....\SQRT.v
.............\.........\.......\TP_RAM.v
.............\.........\.......\VGA_Ctrl.v
.............\.........\.......\vip_rom.qip
.............\.........\.......\vip_rom.v
.............\.........\osd_rom.qip
.............\.........\PLLJ_PLLSPE_INFO.txt
.............\.........\Sdram_PLL.qip
.............\.........\Sdram_RD_FIFO.qip
.............\Reference\Edge Detection Reference.pdf
.............\.........\matlab边缘检测\1.jpg
.............\.........\..............\lena.bmp
.............\.........\..............\lenaOutput.jpg
.............\.........\..............\sobel.m
.............\.........\..............\sobel2.m
.............\.........\sobel.pdf
.............\.........\sobel_edge.c
.............\FPGA_CODE\MY_CODE\mif
.............\.........\.......\Sdram_Control_4Port
.............\.........\.......\Sobel
.............\.........\greybox_tmp
.............\.........\MY_CODE
.............\Reference\matlab边缘检测
.............\FPGA_CODE
.............\Reference
CD1_EDGE_DECT