Description: Use a continue to familiar with ISE and Modelsim, practice in accordance with the experimental manual.
Two write a complete entity and architecture, to construct a 1 bit full adder with logic function, and use ise to check the grammar and
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实验一\adder.vhd
......\adders_4.v
......\adders_4.vhd
......\addertb.vhd
......\divclk1.txt
......\divclk1_tb.txt
......\实验.txt
实验一
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