Description: Please design a 4 bit shift register, requirements are as follows:
1) asynchronous reset
2) synchronous loading
3) to complete the shift left, right. The displacement mode can support the arithmetic, logical, and cyclic displacement.
4) to complete the simulation, prove the function correctly.
5) can see the comprehensive results.
Note: do not need a bit input, parallel output load can also use the parallel output.
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File list (Check if you may need any files):
test3
.....\BIT_VECTOR.txt
.....\STD_LOGIC_VECTOR.txt
.....\shft.txt
.....\shift.txt
.....\shifttb.txt
.....\tb.txt
.....\位移寄存器.txt
.....\位移寄存器2.txt
.....\位移寄存器3.txt
.....\作业要求.txt
.....\功能.docx
.....\原理图.png
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