Description: Using ModelSim Altera design for timing simulation of brief steps 1. Establish project simulation tool options set parameters
2. Use the Quartus II compilation project
3. Establish simulation project
Compilation and mapping 4.Altera emulation library
5. Compile HDL source code and Testbench
6. Start the emulator and the top load design
7. Open the observation window, add signals
8. perform simulation
To Search:
File list (Check if you may need any files):
Example-b8-2\Altera_lib_files\220model.txt
............\................\220model.v
............\................\220model.vhd
............\................\220model_87.vhd
............\................\220pack.vhd
............\................\altera_mf.txt
............\................\altera_mf.v
............\................\altera_mf.vhd
............\................\altera_mf_87.vhd
............\................\altera_mf_components.vhd
............\................\stratix_atoms.v
............\................\stratix_atoms.vhd
............\................\stratix_components.vhd
............\func_sim\dpram8x32.v
............\........\func_sim.cr.mti
............\........\func_sim.mpf
............\........\func_sim_wave.wlf
............\........\pllx2.v
............\........\pll_ram.v
............\........\pll_ram_tb.v
............\........\transcript
............\........\vsim.wlf
............\........\wave.bmp
............\........\wave.do
............\........\.ork\dpram8x32\verilog.asm
............\........\....\.........\_primary.dat
............\........\....\.........\_primary.vhd
............\........\....\pllx2\verilog.asm
............\........\....\.....\_primary.dat
............\........\....\.....\_primary.vhd
............\........\....\..._ram\verilog.asm
............\........\....\.......\_primary.dat
............\........\....\.......\_primary.vhd
............\........\....\......._tb\verilog.asm
............\........\....\..........\_primary.dat
............\........\....\..........\_primary.vhd
............\........\....\_info
............\pll_ram\cmp_state.ini
............\.......\db\altsyncram_7bc1.tdf
............\.......\..\pll_ram.db_info
............\.......\..\pll_ram.eco.cdb
............\.......\..\pll_ram.sld_design_entry.sci
............\.......\..\pll_ram_cmp.qrpt
............\.......\..\pll_ram_hier_info
............\.......\..\pll_ram_syn_hier_info
............\.......\dpram8x32.v
............\.......\pllx2.v
............\.......\pll_ram.asm.rpt
............\.......\pll_ram.done
............\.......\pll_ram.eda.rpt
............\.......\pll_ram.fit.eqn
............\.......\pll_ram.fit.rpt
............\.......\pll_ram.flow.rpt
............\.......\pll_ram.map.eqn
............\.......\pll_ram.map.rpt
............\.......\pll_ram.pin
............\.......\pll_ram.pof
............\.......\pll_ram.qpf
............\.......\pll_ram.qsf
............\.......\pll_ram.qws
............\.......\pll_ram.sof
............\.......\pll_ram.tan.rpt
............\.......\pll_ram.tan.summary
............\.......\pll_ram.v
............\.......\pll_ram_assignment_defaults.qdf
............\.......\simulation\modelsim\pll_ram.vo
............\.......\..........\........\pll_ram_modelsim.xrf
............\.......\..........\........\pll_ram_v.sdo
............\source\dpram8x32.v
............\......\dpram8x32_bb.v
............\......\dpram8x32_wave0.jpg
............\......\dpram8x32_wave1.jpg
............\......\dpram8x32_wave2.jpg
............\......\dpram8x32_wave3.jpg
............\......\dpram8x32_waveforms.html
............\......\pllx2.v
............\......\pllx2_bb.v
............\......\pll_ram.v
............\......\pll_ram_tb.v
............\......\.ost-simulation\modelsim\pll_ram.vo
............\......\...............\........\pll_ram_modelsim.xrf
............\......\...............\........\pll_ram_v.sdo
............\timing_sim\work\@a@l@t@e@r@a_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s\verilog.asm
............\..........\....\..........................................\_primary.dat
............\..........\....\..........................................\_primary.vhd
............\..........\....\.l@p@m_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s\verilog.asm
............\..........\....\....................................\_primary.dat
............\..........\....\....................................\_primary.vhd
............\..........\....\........h@i@n@t_@e@v@a@l@u@a@t@i@o@n\verilog.asm
............\..........\....\....................................\_primary.dat
............\..........\....\....................................\_
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