Description: Under \ Example-s5-1 \ des directory for design engineering, the design input using Synplify precompiled .vqm netlist
\ Example-s5-1 \ source directory for the design of the source code, just to give examples of Verilog language, reference work
\ Example-s5-1 \ source \ area_opt directory for the area-optimized code
Under \ Example-s5-1 \ source \ perf_opt directory for performance-optimized code
Under the \ Example-s5-1 \ source \ common directory is shared code
To Search:
File list (Check if you may need any files):
Example-s5-1\des\cmp_state.ini
............\...\db\des.db_info
............\...\..\des.project.hdb
............\...\.es.bak\des.ssf
............\...\des.qpf
............\...\des.qsf
............\...\des.qws
............\...\des.ssf
............\...\des.vqm
............\source\area_opt\des.v
............\......\........\key_sel.v
............\......\common\crp.v
............\......\......\sbox1.v
............\......\......\sbox2.v
............\......\......\sbox3.v
............\......\......\sbox4.v
............\......\......\sbox5.v
............\......\......\sbox6.v
............\......\......\sbox7.v
............\......\......\sbox8.v
............\......\perf_opt\des.v
............\......\........\key_sel.v
............\示例说明.doc
............\des\db
............\...\des.bak
............\source\area_opt
............\......\common
............\......\perf_opt
............\des
............\source
Example-s5-1
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