- Category:
- VHDL-FPGA-Verilog
- Tags:
-
- File Size:
- 4kb
- Update:
- 2015-03-04
- Downloads:
- 0 Times
- Uploaded by:
- lmy
Description: This program implements the building vhdl UART serial interface on the FPGA. Divided into two parts, UART transfer sender and receiver receiver. Required to provide the baud clock external demand.
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receiver.vhd
transfer.vhd
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