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Title: 8wei7duanshumaguanxianshi Download
  • Category:
  • VHDL-FPGA-Verilog
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  • File Size:
  • 1.09mb
  • Update:
  • 2015-03-23
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  • Uploaded by:
  • pld
 Description: The FPGA development instance of eight seven segment digital tube dynamic display circuit design.
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Example4\db\exp4.asm.qmsg
........\..\exp4.asm_labs.ddb
........\..\exp4.cbx.xml
........\..\exp4.cmp.bpm
........\..\exp4.cmp.cdb
........\..\exp4.cmp.ecobp
........\..\exp4.cmp.hdb
........\..\exp4.cmp.kpt
........\..\exp4.cmp.logdb
........\..\exp4.cmp.rdb
........\..\exp4.cmp_merge.kpt
........\..\exp4.cuda_io_sim_cache.31um_ff_1200mv_0c_fast.hsd
........\..\exp4.cuda_io_sim_cache.31um_ss_1200mv_85c_slow.hsd
........\..\exp4.db_info
........\..\exp4.eco.cdb
........\..\exp4.eda.qmsg
........\..\exp4.fit.qmsg
........\..\exp4.hier_info
........\..\exp4.hif
........\..\exp4.map.bpm
........\..\exp4.map.cdb
........\..\exp4.map.ecobp
........\..\exp4.map.hdb
........\..\exp4.map.kpt
........\..\exp4.map.logdb
........\..\exp4.map.qmsg
........\..\exp4.map_bb.cdb
........\..\exp4.map_bb.hdb
........\..\exp4.map_bb.hdbx
........\..\exp4.map_bb.logdb
........\..\exp4.pre_map.cdb
........\..\exp4.pre_map.hdb
........\..\exp4.psp
........\..\exp4.rtlv.hdb
........\..\exp4.rtlv_sg.cdb
........\..\exp4.rtlv_sg_swap.cdb
........\..\exp4.sgdiff.cdb
........\..\exp4.sgdiff.hdb
........\..\exp4.sld_design_entry.sci
........\..\exp4.sld_design_entry_dsc.sci
........\..\exp4.sta.qmsg
........\..\exp4.sta.rdb
........\..\exp4.sta_cmp.8_slow_1200mv_85c.tdb
........\..\exp4.syn_hier_info
........\..\exp4.tiscmp.fastest_slow_1200mv_0c.ddb
........\..\exp4.tiscmp.fastest_slow_1200mv_85c.ddb
........\..\exp4.tiscmp.fast_1200mv_0c.ddb
........\..\exp4.tiscmp.slow_1200mv_0c.ddb
........\..\exp4.tiscmp.slow_1200mv_85c.ddb
........\..\exp4.tis_db_list.ddb
........\..\exp4.tmw_info
........\..\prev_cmp_exp4.asm.qmsg
........\..\prev_cmp_exp4.eda.qmsg
........\..\prev_cmp_exp4.fit.qmsg
........\..\prev_cmp_exp4.map.qmsg
........\..\prev_cmp_exp4.qmsg
........\..\prev_cmp_exp4.sta.qmsg
........\exp4.asm.rpt
........\exp4.done
........\exp4.eda.rpt
........\exp4.fit.rpt
........\exp4.fit.smsg
........\exp4.fit.summary
........\exp4.flow.rpt
........\exp4.map.rpt
........\exp4.map.summary
........\exp4.pin
........\exp4.qpf
........\exp4.qsf
........\exp4.qws
........\exp4.sof
........\exp4.sta.rpt
........\exp4.sta.summary
........\exp4.vhd
........\exp4.vhd.bak
........\incremental_db\compiled_partitions\exp4.root_partition.cmp.atm
........\..............\...................\exp4.root_partition.cmp.dfp
........\..............\...................\exp4.root_partition.cmp.hdbx
........\..............\...................\exp4.root_partition.cmp.kpt
........\..............\...................\exp4.root_partition.cmp.logdb
........\..............\...................\exp4.root_partition.cmp.rcf
........\..............\...................\exp4.root_partition.map.atm
........\..............\...................\exp4.root_partition.map.dpi
........\..............\...................\exp4.root_partition.map.hdbx
........\..............\...................\exp4.root_partition.map.kpt
........\..............\README
........\simulation\modelsim\exp4.sft
........\..........\........\exp4.vho
........\..........\........\exp4_8_1200mv_0c_vhd_slow.sdo
........\..........\........\exp4_8_1200mv_85c_vhd_slow.sdo
........\..........\........\exp4_min_1200mv_0c_vhd_fast.sdo
........\..........\........\exp4_modelsim.xrf
........\..........\........\exp4_vhd.sdo
........\timing\primetime\exp4.collections.sdc
........\......\.........\exp4.constraints.sdc
........\......\.........\exp4.pt.tcl
........\......\.........\exp4.vo
........\......\.........\exp4_8_1200mv_0c_v_slow.sdo
........\......\.........\exp4_8_1200mv_85c_v_slow.sdo
........\......\.........\exp4_min_1200mv_0c_v_fast.sdo
    

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