Description: Design tasks: Design a crossroads of traffic light control circuit, requiring vehicle lanes and B. A two-lane road cross alternately run. Design requirements: 1. Require bright yellow first five seconds to change lanes and running a red light yellow light by the frequency of 1Hz other roads flashes. 2. Demands that the passage of time and the yellow light time can be set within 60 seconds. 3. Requests the traffic light control circuit can manually control immediately enter the special operation, that two trail-red light, the clock will stop the clock. After the end of the special operation status, system recovery, continue to operate normally.
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....\v3
....\..\Verilog1.asm.rpt
....\..\Verilog1.done
....\..\Verilog1.dpf
....\..\Verilog1.eda.rpt
....\..\Verilog1.fit.rpt
....\..\Verilog1.fit.summary
....\..\Verilog1.flow.rpt
....\..\Verilog1.map.rpt
....\..\Verilog1.map.smsg
....\..\Verilog1.map.summary
....\..\Verilog1.pin
....\..\Verilog1.qpf
....\..\Verilog1.qsf
....\..\Verilog1.qsf.bak
....\..\Verilog1.qws
....\..\Verilog1.sim.rpt
....\..\Verilog1.sof
....\..\Verilog1.sta.rpt
....\..\Verilog1.sta.summary
....\..\Verilog1.v
....\..\Verilog1.v.bak
....\..\Verilog1.vwf
....\..\Waveform1.vwf
....\..\db
....\..\..\Verilog1.asm.qmsg
....\..\..\Verilog1.asm_labs.ddb
....\..\..\Verilog1.cbx.xml
....\..\..\Verilog1.cmp.bpm
....\..\..\Verilog1.cmp.cdb
....\..\..\Verilog1.cmp.ecobp
....\..\..\Verilog1.cmp.hdb
....\..\..\Verilog1.cmp.kpt
....\..\..\Verilog1.cmp.logdb
....\..\..\Verilog1.cmp.rdb
....\..\..\Verilog1.cmp_merge.kpt
....\..\..\Verilog1.cuda_io_sim_cache.31um_ff_1200mv_0c_fast.hsd
....\..\..\Verilog1.cuda_io_sim_cache.31um_tt_1200mv_85c_slow.hsd
....\..\..\Verilog1.db_info
....\..\..\Verilog1.eco.cdb
....\..\..\Verilog1.eda.qmsg
....\..\..\Verilog1.eds_overflow
....\..\..\Verilog1.fit.qmsg
....\..\..\Verilog1.fnsim.cdb
....\..\..\Verilog1.fnsim.hdb
....\..\..\Verilog1.fnsim.qmsg
....\..\..\Verilog1.hier_info
....\..\..\Verilog1.hif
....\..\..\Verilog1.lpc.html
....\..\..\Verilog1.lpc.rdb
....\..\..\Verilog1.lpc.txt
....\..\..\Verilog1.map.bpm
....\..\..\Verilog1.map.cdb
....\..\..\Verilog1.map.ecobp
....\..\..\Verilog1.map.hdb
....\..\..\Verilog1.map.kpt
....\..\..\Verilog1.map.logdb
....\..\..\Verilog1.map.qmsg
....\..\..\Verilog1.map_bb.cdb
....\..\..\Verilog1.map_bb.hdb
....\..\..\Verilog1.map_bb.logdb
....\..\..\Verilog1.pre_map.cdb
....\..\..\Verilog1.pre_map.hdb
....\..\..\Verilog1.rtlv.hdb
....\..\..\Verilog1.rtlv_sg.cdb
....\..\..\Verilog1.rtlv_sg_swap.cdb
....\..\..\Verilog1.sgdiff.cdb
....\..\..\Verilog1.sgdiff.hdb
....\..\..\Verilog1.sim.cvwf
....\..\..\Verilog1.sim.hdb
....\..\..\Verilog1.sim.qmsg
....\..\..\Verilog1.sim.rdb
....\..\..\Verilog1.sld_design_entry.sci
....\..\..\Verilog1.sld_design_entry_dsc.sci
....\..\..\Verilog1.sta.qmsg
....\..\..\Verilog1.sta.rdb
....\..\..\Verilog1.sta_cmp.6_slow_1200mv_85c.tdb
....\..\..\Verilog1.syn_hier_info
....\..\..\Verilog1.tis_db_list.ddb
....\..\..\Verilog1.tiscmp.fast_1200mv_0c.ddb
....\..\..\Verilog1.tiscmp.slow_1200mv_0c.ddb
....\..\..\Verilog1.tiscmp.slow_1200mv_85c.ddb
....\..\..\Verilog1_global_asgn_op.abo
....\..\..\add_sub_unc.tdf
....\..\..\add_sub_vnc.tdf
....\..\..\alt_u_div_t2f.tdf
....\..\..\lpm_divide_8gm.tdf
....\..\..\lpm_divide_b8m.tdf
....\..\..\mux_7qc.tdf
....\..\..\mux_src.tdf
....\..\..\prev_cmp_Verilog1.asm.qmsg
....\..\..\prev_cmp_Verilog1.eda.qmsg
....\..\..\prev_cmp_Verilog1.fit.qmsg
....\..\..\prev_cmp_Verilog1.map.qmsg
....\..\..\prev_cmp_Verilog1.qmsg
....\..\..\prev_cmp_Verilog1.sim.qmsg
....\..\..\prev_cmp_Verilog1.sta.qmsg
....\..\..\sign_div_unsign_9kh.tdf
....\..\..\wed.wsf
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