- Category:
- VHDL-FPGA-Verilog
- Tags:
-
- File Size:
- 8kb
- Update:
- 2015-04-14
- Downloads:
- 0 Times
- Uploaded by:
- 田纪龙
Description: Quartus9 developed a simulation on ASK modulation and demodulation based on the top floor with a schematic, each module using VHDL language
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File list (Check if you may need any files):
ask.bdf
ask.vwf
askcode.bsf
askcode.vhd
askcodec.bsf
askcodec.qpf
askcodec.vhd
askdec.bsf
askdec.vhd
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