- Category:
- VHDL-FPGA-Verilog
- Tags:
-
- File Size:
- 48kb
- Update:
- 2015-04-15
- Downloads:
- 0 Times
- Uploaded by:
- 董扬
Description: This a simple state machine vhdl routines, suitable for beginners to learn, easy to understand.
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cnt5_fsm\cnt5_fsm.asm.rpt
........\cnt5_fsm.done
........\cnt5_fsm.fit.rpt
........\cnt5_fsm.fit.smsg
........\cnt5_fsm.fit.summary
........\cnt5_fsm.flow.rpt
........\cnt5_fsm.map.rpt
........\cnt5_fsm.map.summary
........\cnt5_fsm.pin
........\cnt5_fsm.pof
........\cnt5_fsm.qpf
........\cnt5_fsm.qsf
........\cnt5_fsm.qws
........\cnt5_fsm.sim.rpt
........\cnt5_fsm.sof
........\cnt5_fsm.tan.rpt
........\cnt5_fsm.vhd
........\cnt5_fsm.vwf
........\cnt5_fsm_assignment_defaults.qdf
........\db\cnt5_fsm.db_info
........\..\cnt5_fsm.sim.vwf
........\..\cnt5_fsm.sld_design_entry.sci
........\..\wed.zsf
........\db
cnt5_fsm
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