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Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
Title: SRC Download
 Description: an implementation of Pipelined CPU in verilog
 Downloaders recently: [More information of uploader zyh]
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SRC\ALU.v
...\Decode.v
...\EX.v
...\ff_lib.v
...\ID.v
...\IF.v
...\InstructionROM.v
...\MipsPipelineCPU.v
...\Registers.v
...\transcript
SRC

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