Description: Hdl of dm transmitter baseband processor based design and implementation including work clock master unit pilot insertion length of the training sequence generated data symbol modulated cyclic prefix and windowing IFFT/FFT channel coding scrambling module,
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Transmitter
...........\clock_generator
...........\...............\clock_generator
...........\...............\...............\clk_generator_summary.html
...........\...............\...............\clock_generator.ise
...........\...............\...............\clock_generator.ise_ISE_Backup
...........\...............\...............\clock_generator.restore
...........\...............\...............\clock_generator.v
...........\...............\...............\clock_generator_summary.html
...........\...............\...............\DCM1.xaw
...........\...............\...............\_xmsgs
...........\CP_ADDER
...........\........\bram1I.asy
...........\........\bram1i.edn
...........\........\bram1i.sym
...........\........\bram1i.v
...........\........\bram1i.veo
...........\........\bram1i.vhd
...........\........\bram1i.vho
...........\........\bram1i.xco
...........\........\bram1r.asy
...........\........\bram1r.edn
...........\........\bram1r.sym
...........\........\bram1r.v
...........\........\bram1r.veo
...........\........\bram1r.vhd
...........\........\bram1r.vho
...........\........\bram1r.xco
...........\........\bram2i.asy
...........\........\bram2i.edn
...........\........\bram2i.sym
...........\........\bram2i.v
...........\........\bram2i.veo
...........\........\bram2i.vhd
...........\........\bram2i.vho
...........\........\bram2i.xco
...........\........\bram2r.asy
...........\........\bram2r.edn
...........\........\bram2r.sym
...........\........\bram2r.v
...........\........\bram2r.veo
...........\........\bram2r.vhd
...........\........\bram2r.vho
...........\........\bram2r.xco
...........\........\CP_ADDER.ise
...........\........\CP_ADDER.ise_ISE_Backup
...........\........\CP_ADDER.restore
...........\........\CP_adder.v
...........\........\CP_adder_summary.html
...........\........\templates
...........\........\.........\coregen.xml
...........\........\_xmsgs
...........\DATA_16QAM_MAP
...........\..............\DATA_16AM_MAP.ise
...........\..............\DATA_16AM_MAP.ise_ISE_Backup
...........\..............\DATA_16AM_MAP.restore
...........\..............\DATA_16QAM_MAP.v
...........\..............\DATA_16QAM_mapper_summary.html
...........\..............\DATA_16QAM_MAP_summary.html
...........\..............\_xmsgs
...........\DATA_CONV_encode
...........\................\conv_encoder.v
...........\................\DATA_CONV_encode.ise
...........\................\DATA_CONV_encode.ise_ISE_Backup
...........\................\DATA_CONV_encode.restore
...........\................\DATA_Conv_encode.v
...........\................\DATA_conv_encoder_summary.html
...........\................\DATA_Conv_encode_summary.html
...........\................\_xmsgs
...........\data_interleaver
...........\................\data_interleaver
...........\................\................\count24.asy
...........\................\................\count24.edn
...........\................\................\count24.sym
...........\................\................\count24.v
...........\................\................\count24.veo
...........\................\................\count24.vhd
...........\................\................\count24.vho
...........\................\................\count24.xco
...........\................\................\data_interleaver.ise
...........\................\................\data_interleaver.ise_ISE_Backup
...........\................\................\data_interleaver.restore
...........\................\................\data_interleaver.v
...........\................\................\data_interleaver_summary.html
...........\................\................\dint_ram.asy
...........\................\................\dint_ram.edn
...........\................\................\dint_ram.sym
...........\................\................\dint_ram.v
...........\................\................\dint_ram.veo
...........\................\................\dint_ram.vhd
...........\................\................\dint_ram.vho
...........\................\................\