Description: The example design of RISC-CPU bus architecture uses a data line (8) and command line (12) is separated with the Harvard architecture, the storage register addressing uses RAM as a register to facilitate programming.
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risc8
.....\alu.v
.....\basic.rom
.....\chart
.....\.....\Thumbs.db
.....\.....\图13-11.bmp
.....\.....\图13-13.bmp
.....\.....\图13-15.bmp
.....\.....\图13-16.bmp
.....\.....\图13-17.bmp
.....\.....\图13-18.bmp
.....\.....\图13-20.bmp
.....\.....\图13-6.bmp
.....\.....\图13-7.bmp
.....\.....\图13-9.bmp
.....\.....\表13-1.bmp
.....\cpu.v
.....\cpu_test.v
.....\dram.v
.....\exp.v
.....\idec.v
.....\pram.v
.....\regs.v
.....\risc8.cr.mti
.....\risc8.mpf
.....\risc8.vcd
.....\sindata.hex
.....\transcript
.....\vsim.wlf
.....\wave
.....\....\Thumbs.db
.....\....\alu.bmp
.....\....\cpu-1.bmp
.....\....\cpu-2.bmp
.....\....\cpu_test.bmp
.....\....\exp.bmp
.....\....\idec.bmp
.....\....\pram.bmp
.....\....\regs.bmp
.....\work
.....\....\_info
.....\....\alu
.....\....\...\_primary.dat
.....\....\...\_primary.vhd
.....\....\...\verilog.asm
.....\....\cpu
.....\....\...\_primary.dat
.....\....\...\_primary.vhd
.....\....\...\verilog.asm
.....\....\cpu_test
.....\....\........\_primary.dat
.....\....\........\_primary.vhd
.....\....\........\verilog.asm
.....\....\dram
.....\....\....\_primary.dat
.....\....\....\_primary.vhd
.....\....\....\verilog.asm
.....\....\exp
.....\....\...\_primary.dat
.....\....\...\_primary.vhd
.....\....\...\verilog.asm
.....\....\idec
.....\....\....\_primary.dat
.....\....\....\_primary.vhd
.....\....\....\verilog.asm
.....\....\pram
.....\....\....\_primary.dat
.....\....\....\_primary.vhd
.....\....\....\verilog.asm
.....\....\regs
.....\....\....\_primary.dat
.....\....\....\_primary.vhd
.....\....\....\verilog.asm
.....\....\risc8.vcd
.....\....\test
.....\....\....\_primary.dat
.....\....\....\_primary.vhd
.....\....\....\verilog.asm
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