Description: Through the SPI interface to a period of 16 length is 8-bit wide configuration register assignment. These configuration registers are readable and writable. And to prepare excitation test, read-after-write, verify functional correctness. Specific requirements SPI interface circuit as follows:
(1) the input signal is a global reset signal reset, chip signal cs, serial input clock signal sclk, serial data input signal and a serial data output signal sdi sdo.
(2) Each transmission cycle time 16-bit data transfer. A total of 24 bits of data transmission in each transmission cycle, wherein the top two bits 10:00 indicates a read operation, the top two bits 11:00 represented a write operation, then six bits represent address information, and then the next the 16 bits of data representing information
To Search:
File list (Check if you may need any files):
mspi
....\mspi.v
....\mspi_tb.v
Download