- Category:
- VHDL-FPGA-Verilog
- Tags:
-
- File Size:
- 3kb
- Update:
- 2016-01-11
- Downloads:
- 0 Times
- Uploaded by:
- cpf
Description: Achieve PWM output dead time control, can guarantee to avoid simultaneous conduction of upper and lower leg damage power devices
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PWM死区控制\dead_zone.bdf
...........\deadz.vhd
PWM死区控制