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Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
Title: reg Download
 Description: 8-bit Shift-Left Register with Positive-Edge Clock, Synchronous Parallel Load, Serial In, and Serial Out
 Downloaders recently: [More information of uploader evgesha]
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reg\shift_registers_7.v
...\shift_registers_7.vhd
reg

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