Description: Reset ASIC design problem is a key issue, which handled properly or not will directly affect the performance of the entire circuit, in this article many angles synchronous reset and asynchronous reset are discussed and analyzed, and compare their advantages and disadvantages focus on the method of synchronization and reset distribution buffer tree two resetting the corresponding solutions for asynchronous reset metastable problem existing in the process.
To Search:
File list (Check if you may need any files):
ASIC设计中的同步复位与异步复位_盛娜.pdf
Download