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Title: PCIE_14_Complete Download
 Description: IP core for PCIE of FPGA,able to simulate with modelsim and check the signal
 Downloaders recently: [More information of uploader terran2831]
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PCIE_14_Complete\PCIE\ipcore_dir\coregen.cgp
................\....\..........\coregen.log
................\....\..........\create_PCIE.tcl
................\....\..........\iseconfig\PCIE.projectmgr
................\....\..........\.........\PCIE.xreport
................\....\..........\PCIE\doc\v6_pcie_ds715.pdf
................\....\..........\....\...\v6_pcie_ug517.pdf
................\....\..........\....\example_design\BMD.v
................\....\..........\....\..............\BMD_64_RX_ENGINE.v
................\....\..........\....\..............\BMD_64_TX_ENGINE.v
................\....\..........\....\..............\BMD_CFG_CTRL.v
................\....\..........\....\..............\BMD_EP.v
................\....\..........\....\..............\BMD_EP_MEM.v
................\....\..........\....\..............\BMD_EP_MEM_ACCESS.v
................\....\..........\....\..............\BMD_GEN2.v
................\....\..........\....\..............\BMD_INTR_CTRL.v
................\....\..........\....\..............\BMD_INTR_CTRL_DELAY.v
................\....\..........\....\..............\BMD_PCIE_20.v
................\....\..........\....\..............\BMD_RD_THROTTLE.v
................\....\..........\....\..............\BMD_TO_CTRL.v
................\....\..........\....\..............\v6_pci_exp_64b_app.v
................\....\..........\....\..............\xilinx_pcie_2_0_ep_v6.v
................\....\..........\....\implement\implement.bat
................\....\..........\....\.........\implement.sh
................\....\..........\....\.........\xilinx_pcie_2_0_ep_v6.cmd
................\....\..........\....\.........\xilinx_pcie_2_0_ep_v6.prj
................\....\..........\....\.........\xilinx_pcie_2_0_ep_v6.xcf
................\....\..........\....\simulation\dsport\pcie_2_0_rport_v6.v
................\....\..........\....\..........\......\pci_exp_expect_tasks.v
................\....\..........\....\..........\......\pci_exp_usrapp_cfg.v
................\....\..........\....\..........\......\pci_exp_usrapp_com.v
................\....\..........\....\..........\......\pci_exp_usrapp_pl.v
................\....\..........\....\..........\......\pci_exp_usrapp_rx.v
................\....\..........\....\..........\......\pci_exp_usrapp_tx.v
................\....\..........\....\..........\......\xilinx_pcie_2_0_rport_v6.v
................\....\..........\....\..........\functional\board.f
................\....\..........\....\..........\..........\board.v
................\....\..........\....\..........\..........\board_common.v
................\....\..........\....\..........\..........\error.dat
................\....\..........\....\..........\..........\isim_cmd.tcl
................\....\..........\....\..........\..........\rx.dat
................\....\..........\....\..........\..........\sim.do
................\....\..........\....\..........\..........\simulate_isim.bat
................\....\..........\....\..........\..........\simulate_isim.sh
................\....\..........\....\..........\..........\simulate_ncsim.sh
................\....\..........\....\..........\..........\simulate_vcs.sh
................\....\..........\....\..........\..........\sys_clk_gen.v
................\....\..........\....\..........\..........\sys_clk_gen_ds.v
................\....\..........\....\..........\..........\tx.dat
................\....\..........\....\..........\..........\vsim.wlf
................\....\..........\....\..........\..........\wave.wcfg
................\....\..........\....\..........\..........\.ork\@_opt\_lib.qdb
................\....\..........\....\..........\..........\....\.....\_lib1_0.qdb
................\....\..........\....\..........\..........\....\.....\_lib1_0.qpg
................\....\..........\....\..........\..........\....\.....\_lib2_0.qdb
................\....\..........\....\..........\..........\....\.....\_lib2_0.qpg
................\....\..........\....\..........\..........\....\.....\_lib3_0.qdb
................\....\..........\....\..........\..........\....\...

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