ethernet\project\c5_pin_model_dump.txt
........\.......\db\.cmp.kpt
........\.......\..\altsyncram_v912.tdf
........\.......\..\ddio_out_b2j.tdf
........\.......\..\ddio_out_e2j.tdf
........\.......\..\logic_util_heursitic.dat
........\.......\..\prev_cmp_TOP.qmsg
........\.......\..\TOP.cmp.rdb
........\.......\..\TOP.db_info
........\.......\..\TOP.eco.cdb
........\.......\..\TOP.ipinfo
........\.......\..\TOP.map.qmsg
........\.......\..\TOP.pti_db_list.ddb
........\.......\..\TOP.sld_design_entry.sci
........\.......\..\TOP.tis_db_list.ddb
........\.......\greybox_tmp\cbx_args.txt
........\.......\incremental_db\compiled_partitions\TOP.db_info
........\.......\..............\README
........\.......\.p_core\DDIO_TXD.ppf
........\.......\.......\DDIO_TXD.qip
........\.......\.......\DDIO_TXD.v
........\.......\.......\DDIO_TXEN.ppf
........\.......\.......\DDIO_TXEN.qip
........\.......\.......\DDIO_TXEN.v
........\.......\.......\PLL_125\PLL_125_0002.qip
........\.......\.......\.......\PLL_125_0002.v
........\.......\.......\PLL_125.bsf
........\.......\.......\PLL_125.cmp
........\.......\.......\PLL_125.ppf
........\.......\.......\PLL_125.qip
........\.......\.......\PLL_125.sip
........\.......\.......\PLL_125.spd
........\.......\.......\PLL_125.v
........\.......\.......\......._sim\aldec\rivierapro_setup.tcl
........\.......\.......\...........\cadence\cds.lib
........\.......\.......\...........\.......\hdl.var
........\.......\.......\...........\.......\ncsim_setup.sh
........\.......\.......\...........\mentor\msim_setup.tcl
........\.......\.......\...........\PLL_125.vo
........\.......\.......\...........\synopsys\vcs\vcs_setup.sh
........\.......\.......\...........\........\...mx\synopsys_sim.setup
........\.......\.......\...........\........\.....\vcsmx_setup.sh
........\.......\.......\PLL_125_sim.f
........\.......\.......\RAM_4x256.qip
........\.......\.......\RAM_4x256.v
........\.......\.......\RAM_4x256_inst.v
........\.......\output_files\TOP.asm.rpt
........\.......\............\TOP.done
........\.......\............\TOP.fit.rpt
........\.......\............\TOP.fit.smsg
........\.......\............\TOP.fit.summary
........\.......\............\TOP.flow.rpt
........\.......\............\TOP.jdi
........\.......\............\TOP.map.rpt
........\.......\............\TOP.map.summary
........\.......\............\TOP.pin
........\.......\............\TOP.sld
........\.......\............\TOP.sof
........\.......\............\TOP.sta.rpt
........\.......\............\TOP.sta.summary
........\.......\PLLJ_PLLSPE_INFO.txt
........\.......\PLL_125.xml
........\.......\TOP.qpf
........\.......\TOP.qsf
........\.......\TOP.qws
........\sourec\ARP_RLY.v
........\......\GEN_CRC.v
........\......\ICMP_CHECK_SUM.v
........\......\ICMP_RLY.v
........\......\REC_FRAME.v
........\......\RGMII_IO.v
........\......\TOP.v
........\project\ip_core\PLL_125_sim\synopsys\vcs
........\.......\.......\...........\........\vcsmx
........\.......\.......\...........\aldec
........\.......\.......\...........\cadence
........\.......\.......\...........\mentor
........\.......\.......\...........\synopsys
........\.......\.ncremental_db\compiled_partitions
........\.......\.p_core\PLL_125
........\.......\.......\PLL_125_sim
........\.......\db
........\.......\greybox_tmp
........\.......\incremental_db
........\.......\ip_core
........\.......\output_files
........\project
........\sourec
ethernet