Description: to increase the speed/Performance of the system the
UT (Urdhva Triyambhayam) multiplier is used. UT Multiplier
[10] is an cient methodology of Indian mathematics as it
contains 16 SUTRAS (formulae). A high speed multiplier
design by using Urdhva Triyambhayam sutra is proposed. By
using this sutra the partial products and sums are generated in
one step which reduces the design of architecture in
processors. By using this sutra we can reduce the time with
high extent when compare
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