ppmu\component\Actel\DirectCore\COREUART\5.1.102\coreparameters.v
....\.........\.....\..........\........\.......\COREUART.cxf
....\.........\work\ppmhfd\ppmhfd.cxf
....\.........\....\......\ppmhfd.sdb
....\.........\....\......\ppmhfd.v
....\.........\....\......\testbench.v
....\.........\....\uare\testbench.v
....\.........\....\....\uare.cxf
....\.........\....\....\uare.sdb
....\.........\....\....\uare.v
....\.........\....\....\...._0\mti\scripts\wave_vlog.do
....\.........\....\....\......\rtl\vlog\core_obfuscated\Clock_gen.v
....\.........\....\....\......\...\....\...............\CoreUART.v
....\.........\....\....\......\...\....\...............\fifo_256x8_pa3.v
....\.........\....\....\......\...\....\...............\Rx_async.v
....\.........\....\....\......\...\....\...............\Tx_async.v
....\.........\....\....\......\...\....\test\user\testbnch.v
....\.........\....\....\......\uare_uare_0_COREUART.cxf
....\.........\....\...tb\testbench.v
....\.........\....\.....\uartb.cxf
....\.........\....\.....\uartb.sdb
....\.........\....\.....\uartb.v
....\.........\....\.....\....._0\mti\scripts\wave_vlog.do
....\.........\....\.....\.......\rtl\vlog\core_obfuscated\Clock_gen.v
....\.........\....\.....\.......\...\....\...............\CoreUART.v
....\.........\....\.....\.......\...\....\...............\fifo_256x8_pa3.v
....\.........\....\.....\.......\...\....\...............\Rx_async.v
....\.........\....\.....\.......\...\....\...............\Tx_async.v
....\.........\....\.....\.......\...\....\test\user\testbnch.v
....\.........\....\.....\.......\uartb_uartb_0_COREUART.cxf
....\..nstraint\aa.pdc
....\..........\aaa.pdc
....\..........\aaaa.pdc
....\..........\cc.sdc
....\..........\data\aa.pdc.ce
....\..........\....\aaa.pdc.ce
....\..........\....\aaaa.pdc.ce
....\designer\impl1\ada02288-1.tmp
....\........\.....\ada03252-1.tmp
....\........\.....\af0.ini
....\........\.....\af2.hdr
....\........\.....\bytec.ide_des
....\........\.....\data.ide_des
....\........\.....\datac.ide_des
....\........\.....\datacc.ide_des
....\........\.....\delay.ide_des
....\........\.....\designer.log
....\........\.....\designer_synth_check.log
....\........\.....\fifo.ide_des
....\........\.....\in.ide_des
....\........\.....\initialsys.ide_des
....\........\.....\pllcc.ide_des
....\........\.....\ppm.ide_des
....\........\.....\ppmde.ide_des
....\........\.....\ppmhfd.adb
....\........\.....\.......dtf\constraints
....\........\.....\..........\inverted_ports
....\........\.....\..........\last_placement.gcf
....\........\.....\..........\masks
....\........\.....\..........\masks.final
....\........\.....\..........\mem_plmt.gcf
....\........\.....\..........\place.log
....\........\.....\..........\route.log
....\........\.....\..........\swloc
....\........\.....\..........\terackt
....\........\.....\..........\teralib
....\........\.....\..........\terapld
....\........\.....\..........\terapld.final
....\........\.....\..........\typeFile
....\........\.....\..........\verify.log
....\........\.....\ppmhfd.ide_des
....\........\.....\ppmhfd.lok
....\........\.....\ppmhfd.pdb
....\........\.....\ppmhfd.pdb.depends
....\........\.....\ppmhfd.tcl
....\........\.....\ppmhfda.pdb
....\........\.....\ppmhfda.pdb.depends
....\........\.....\ppmhfd_1.adb
....\........\.....\.........dtf\verify.log
....\........\.....\ppmhfd_1.ide_des
....\........\.....\ppmhfd_1.pdb
....\........\.....\ppmhfd_1.pdb.depends
....\........\.....\........_fp\$$FlashPro_FPBBALTLPT1.L$$
....\........\.....\...........\ppmhfd_1.log
....\........\.....\...........\ppmhfd_1.pro
....\........\.....\...........\.rojectData\ppmhfd_1.pdb
....\........\.....\..........._1\$$FlashPro_FPBBALTLPT1.L$$
....\........\.....\.............\ppmhfd_1.log
....\........\.....\.............\ppmhfd_1.pro
....\........\.....\.............\.rojectData\ppmhfd_1.pdb
....\........\.....\ppmhfd_1_iteration_summary.rpt
....\........\.....\ppmhfd_1_layout.log
....\........\.....\ppmhfd_1_power.rpt
....\........\.....\ppmhfd_1_power_r1_initial.rpt
....\........\..