- Category:
- VHDL-FPGA-Verilog
- Tags:
-
- File Size:
- 223kb
- Update:
- 2016-12-27
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- Uploaded by:
- 小方
Description: The experiment task is to use Quartus II software, text input, generates a basic flip-flop, flip-flop may be a form, you can also structure NAND gate NOR gate structure. Use the key experiment using key module 7 and 8 keys to represent the R and S, with LED D1 and LED D2 LED module respectively Q and Q. In the case of R and S satisfy the formula (2) under observation Q and Q change.
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实验3
.....\RSFF2.asm.rpt
.....\RSFF2.cdf
.....\RSFF2.done
.....\RSFF2.fit.eqn
.....\RSFF2.fit.rpt
.....\RSFF2.fit.summary
.....\RSFF2.flow.rpt
.....\RSFF2.map.eqn
.....\RSFF2.map.rpt
.....\RSFF2.map.summary
.....\RSFF2.pin
.....\RSFF2.pof
.....\RSFF2.qpf
.....\RSFF2.qsf
.....\RSFF2.qws
.....\RSFF2.sim.rpt
.....\RSFF2.sof
.....\RSFF2.tan.rpt
.....\RSFF2.tan.summary
.....\RSFF2.vhd
.....\RSFF2.vwf
.....\db
.....\..\RSFF2.asm.qmsg
.....\..\RSFF2.asm_labs.ddb
.....\..\RSFF2.cbx.xml
.....\..\RSFF2.cmp.cdb
.....\..\RSFF2.cmp.hdb
.....\..\RSFF2.cmp.logdb
.....\..\RSFF2.cmp.qrpt
.....\..\RSFF2.cmp.rdb
.....\..\RSFF2.cmp.tdb
.....\..\RSFF2.cmp0.ddb
.....\..\RSFF2.cmp2.ddb
.....\..\RSFF2.db_info
.....\..\RSFF2.dbp
.....\..\RSFF2.eco.cdb
.....\..\RSFF2.eds_overflow
.....\..\RSFF2.fit.qmsg
.....\..\RSFF2.hier_info
.....\..\RSFF2.hif
.....\..\RSFF2.map.cdb
.....\..\RSFF2.map.hdb
.....\..\RSFF2.map.logdb
.....\..\RSFF2.map.qmsg
.....\..\RSFF2.pre_map.cdb
.....\..\RSFF2.pre_map.hdb
.....\..\RSFF2.psp
.....\..\RSFF2.rtlv.hdb
.....\..\RSFF2.rtlv_sg.cdb
.....\..\RSFF2.rtlv_sg_swap.cdb
.....\..\RSFF2.sgdiff.cdb
.....\..\RSFF2.sgdiff.hdb
.....\..\RSFF2.signalprobe.cdb
.....\..\RSFF2.sim.hdb
.....\..\RSFF2.sim.qmsg
.....\..\RSFF2.sim.qrpt
.....\..\RSFF2.sim.rdb
.....\..\RSFF2.sim.vwf
.....\..\RSFF2.sld_design_entry.sci
.....\..\RSFF2.sld_design_entry_dsc.sci
.....\..\RSFF2.syn_hier_info
.....\..\RSFF2.tan.qmsg
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