- Category:
- VHDL-FPGA-Verilog
- Tags:
-
- File Size:
- 266kb
- Update:
- 2016-12-27
- Downloads:
- 0 Times
- Uploaded by:
- 小方
Description: This experiment requires the completion of a two-decimal counter and through digital static display. In the experiment, the system clock is selected as the input clock (clk) ,, two key input, key 8 when high, reset, when the low key 8, when the key 7 high proceeds can count, the number counted in the digital display.
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test4
.....\cnt20.asm.rpt
.....\cnt20.done
.....\cnt20.fit.eqn
.....\cnt20.fit.rpt
.....\cnt20.fit.summary
.....\cnt20.flow.rpt
.....\cnt20.map.eqn
.....\cnt20.map.rpt
.....\cnt20.map.summary
.....\cnt20.pin
.....\cnt20.pof
.....\cnt20.qpf
.....\cnt20.qsf
.....\cnt20.qws
.....\cnt20.sim.rpt
.....\cnt20.sof
.....\cnt20.tan.rpt
.....\cnt20.tan.summary
.....\cnt20.vhd
.....\cnt20.vwf
.....\db
.....\..\cnt20.asm.qmsg
.....\..\cnt20.asm_labs.ddb
.....\..\cnt20.cbx.xml
.....\..\cnt20.cmp.cdb
.....\..\cnt20.cmp.hdb
.....\..\cnt20.cmp.logdb
.....\..\cnt20.cmp.qrpt
.....\..\cnt20.cmp.rdb
.....\..\cnt20.cmp.tdb
.....\..\cnt20.cmp0.ddb
.....\..\cnt20.cmp2.ddb
.....\..\cnt20.db_info
.....\..\cnt20.dbp
.....\..\cnt20.eco.cdb
.....\..\cnt20.eds_overflow
.....\..\cnt20.fit.qmsg
.....\..\cnt20.hier_info
.....\..\cnt20.hif
.....\..\cnt20.map.cdb
.....\..\cnt20.map.hdb
.....\..\cnt20.map.logdb
.....\..\cnt20.map.qmsg
.....\..\cnt20.pre_map.cdb
.....\..\cnt20.pre_map.hdb
.....\..\cnt20.psp
.....\..\cnt20.rtlv.hdb
.....\..\cnt20.rtlv_sg.cdb
.....\..\cnt20.rtlv_sg_swap.cdb
.....\..\cnt20.sgdiff.cdb
.....\..\cnt20.sgdiff.hdb
.....\..\cnt20.signalprobe.cdb
.....\..\cnt20.sim.hdb
.....\..\cnt20.sim.qmsg
.....\..\cnt20.sim.qrpt
.....\..\cnt20.sim.rdb
.....\..\cnt20.sim.vwf
.....\..\cnt20.sld_design_entry.sci
.....\..\cnt20.sld_design_entry_dsc.sci
.....\..\cnt20.syn_hier_info
.....\..\cnt20.tan.qmsg
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