Description: RS (255223) encoding and decoding algorithm. VerilogHDL code to achieve, in the XILINX chip to be verified. Does not contain any IP core, easy to transplant to any FPGA chip.
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RS_Encode_Decode
................\resource
................\........\GF_invers_rom.v
................\........\readme.txt
................\........\RS_BM_Decode.v
................\........\RS_Encode.v
................\........\RS_Encode_Decode.v
................\........\RS_Encode_Decode_Testbench.v
................\........\RS_fifo.v
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