- Category:
- VHDL-FPGA-Verilog
- Tags:
-
- File Size:
- 1kb
- Update:
- 2016-02-21
- Downloads:
- 0 Times
- Uploaded by:
- 小白
Description: Clock divider function module, after using two different counter or re-shift ways to save resources.
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clk_div.vhd