VGA实验_v1.docx
file_vga
........\vga.v
........\vga.xdc
lab_vga
.......\lab_vga.cache
.......\.............\wt
.......\.............\..\synthesis.wdf
.......\.............\..\webtalk_pa.xml
.......\lab_vga.runs
.......\............\.jobs
.......\............\.....\vrs_config_1.xml
.......\............\.....\vrs_config_2.xml
.......\............\.....\vrs_config_3.xml
.......\............\clk_wiz_0_synth_1
.......\............\.................\.Vivado Synthesis.queue.rst
.......\............\.................\.Xil
.......\............\.................\....\clk_wiz_0_propImpl.xdc
.......\............\.................\.vivado.begin.rst
.......\............\.................\.vivado.end.rst
.......\............\.................\ISEWrap.js
.......\............\.................\ISEWrap.sh
.......\............\.................\clk_wiz_0.dcp
.......\............\.................\clk_wiz_0.tcl
.......\............\.................\clk_wiz_0.vds
.......\............\.................\clk_wiz_0_utilization_synth.pb
.......\............\.................\clk_wiz_0_utilization_synth.rpt
.......\............\.................\dont_touch.xdc
.......\............\.................\gen_run.xml
.......\............\.................\htr.txt
.......\............\.................\project.wdf
.......\............\.................\rundef.js
.......\............\.................\runme.bat
.......\............\.................\runme.log
.......\............\.................\runme.sh
.......\............\.................\vivado.jou
.......\............\.................\vivado.pb
.......\............\impl_1
.......\............\......\.Vivado Implementation.queue.rst
.......\............\......\.Xil
.......\............\......\.init_design.begin.rst
.......\............\......\.init_design.end.rst
.......\............\......\.opt_design.begin.rst
.......\............\......\.opt_design.end.rst
.......\............\......\.place_design.begin.rst
.......\............\......\.place_design.end.rst
.......\............\......\.route_design.begin.rst
.......\............\......\.route_design.end.rst
.......\............\......\.vivado.begin.rst
.......\............\......\.vivado.end.rst
.......\............\......\.write_bitstream.begin.rst
.......\............\......\.write_bitstream.end.rst
.......\............\......\ISEWrap.js
.......\............\......\ISEWrap.sh
.......\............\......\gen_run.xml
.......\............\......\htr.txt
.......\............\......\init_design.pb
.......\............\......\opt_design.pb
.......\............\......\place_design.pb
.......\............\......\project.wdf
.......\............\......\route_design.pb
.......\............\......\rundef.js
.......\............\......\runme.bat
.......\............\......\runme.log
.......\............\......\runme.sh
.......\............\......\usage_statistics_webtalk.html
.......\............\......\usage_statistics_webtalk.xml
.......\............\......\vga.bit
.......\............\......\vga.tcl
.......\............\......\vga.vdi
.......\............\......\vga_clock_utilization_placed.rpt
.......\............\......\vga_control_sets_placed.rpt
.......\............\......\vga_drc_routed.pb
.......\............\......\vga_drc_routed.rpt
.......\............\......\vga_io_placed.rpt
.......\............\......\vga_opt.dcp
.......\............\......\vga_placed.dcp
.......\............\......\vga_power_routed.rpt
.......\............\......\vga_power_summary_routed.pb
.......\............\......\vga_route_status.pb
.......\............\......\vga_route_status.rpt
.......\............\......\vga_routed.dcp
.......\............\......\vga_timing_summary_routed.pb
.......\............\......\vga_timing_summary_routed.rpt
.......\............\......\vga_utilization_placed.pb
.......\............\......\vga_utilization_placed.rpt
.......\............\......\vivado.jou
.......\............\......\vivado.pb
.......\............\......\write_bitstream.pb
.......\............\synth_1
.......\............\.......\.Vivado Synthesis.queue.rst
.......\......