- Category:
- Other systems
- Tags:
-
- File Size:
- 1kb
- Update:
- 2016-03-14
- Downloads:
- 0 Times
- Uploaded by:
- 胡生
Description: When do synthesis, Design Compiler will optimize the tie 0 ports as default. This tool/script can keep the tie 0 ports in the output netlist.
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File list (Check if you may need any files):
remove_dc_input_tieoffs.tcl
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