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Title: uart2bus_latest Download
 Description: uart IP
 Downloaders recently: [More information of uploader andrew.zhang]
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uart2bus_latest\uart2bus\Baud Calc.xlsx
...............\........\trunk\doc\UART to Bus Core Specifications.pdf
...............\........\.....\scilab\calc_baud_gen.sce
...............\........\.....\verilog\bench\reg_file_model.v
...............\........\.....\.......\.....\tb_bin_uart2bus_top.v
...............\........\.....\.......\.....\tb_txt_uart2bus_top.v
...............\........\.....\.......\.....\tb_uart2bus_top.v
...............\........\.....\.......\.....\timescale.v
...............\........\.....\.......\.....\uart_tasks.v
...............\........\.....\.......\rtl\baud_gen.v
...............\........\.....\.......\...\uart2bus_top.v
...............\........\.....\.......\...\uart_parser.v
...............\........\.....\.......\...\uart_rx.v
...............\........\.....\.......\...\uart_top.v
...............\........\.....\.......\...\uart_tx.v
...............\........\.....\.......\sim\icarus\block_bin.cfg
...............\........\.....\.......\...\......\block_txt.cfg
...............\........\.....\.......\...\......\compile_bin.bat
...............\........\.....\.......\...\......\compile_txt.bat
...............\........\.....\.......\...\......\gtk.bat
...............\........\.....\.......\...\......\run.bat
...............\........\.....\.......\...\......\test.bin
...............\........\.....\.......\...\......\test.txt
...............\........\.....\.......\.yn\altera\uart2bus.qpf
...............\........\.....\.......\...\......\uart2bus.qws
...............\........\.....\.......\...\......\uart2bus_top.qsf
...............\........\.....\.......\...\xilinx\iseconfig\uart2bus.projectmgr
...............\........\.....\.......\...\......\.........\uart2bus_top.xreport
...............\........\.....\.......\...\......\uart2bus.gise
...............\........\.....\.......\...\......\uart2bus.xise
...............\........\.....\.......\...\......\uart2bus_top_summary.html
...............\........\.....\.......\...\......\_xmsgs\pn_parser.xmsgs
...............\........\.....\.hdl\bench\helpers\helpers_pkg.vhd
...............\........\.....\....\.....\.......\regFileModel.vhd
...............\........\.....\....\.....\uart2BusTop_bin_tb.vhd
...............\........\.....\....\.....\uart2BusTop_txt_tb.vhd
...............\........\.....\....\rtl\baudGen.vhd
...............\........\.....\....\...\uart2BusTop.vhd
...............\........\.....\....\...\uart2BusTop_pkg.vhd
...............\........\.....\....\...\uartParser.vhd
...............\........\.....\....\...\uartRx.vhd
...............\........\.....\....\...\uartTop.vhd
...............\........\.....\....\...\uartTx.vhd
...............\........\.....\....\sim\ghdl\shell_tools.sh
...............\........\.....\....\...\....\uart2BusTop_bin_tb.sav
...............\........\.....\....\...\....\uart2BusTop_txt_tb.sav
...............\........\.....\....\...\....\uart2bus_bin_build.sh
...............\........\.....\....\...\....\uart2bus_txt_build.sh
...............\........\.....\....\...\modelsim\uart2bus_bin_sim.bat
...............\........\.....\....\...\........\uart2bus_bin_sim.tcl
...............\........\.....\....\...\........\uart2bus_txt_sim.bat
...............\........\.....\....\...\........\uart2bus_txt_sim.tcl
...............\........\.....\....\...\........\wave_uart2bus_bin.do
...............\........\.....\....\...\........\wave_uart2bus_txt.do
...............\........\.....\....\...\test.bin
...............\........\.....\....\...\test.txt
...............\........\.....\....\.yn\xilinx\uart2bus.xise
...............\........\.....\.erilog\syn\xilinx\iseconfig
...............\........\.....\.......\...\......\_xmsgs
...............\........\.....\.......\.im\icarus
...............\........\.....\.......\.yn\altera
...............\........\.....\.......\...\xilinx
...............\........\.....\.hdl\bench\helpers
...............\........\.....\....\sim\ghdl
...............\........\.....\....\...\modelsim
...............\........\.....\....\.yn\xilinx
...............\........\.....\.erilog\bench
...............\........\.....\.......\rtl
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